Memory macro with irregular edge cells

ABSTRACT

A memory macro includes a first set of cells disposed in a first area of a memory array, and a second set of cells, which differ from the first set of cells in physical dimensions, disposed at an edge of the first area for improving robustness of the cells at the edge of the memory array.

BACKGROUND

The present invention relates generally to integrated circuit (IC)designs, and more particularly to a memory macro with irregular edgecells.

The rapid growth in complexity of modern electronic circuits has forcedelectronic circuit designers to rely upon computer programs to assist orautomate most steps of the design process. A typical circuit designcontains hundreds of thousands or millions of individual pieces or “leafcells” or “cells.” Such design is too large for a circuit designer oreven a team of designers to manage manually. Thus, a memory compiler isoften used to facilitate memory designs. A typical memory compiler is aset of various, parameterized generators that can help designers to layout memory macros, such as dynamic random access memory (DRAM) macros orstatic random access memory (SRAM) macros.

Conventionally, all cells in a memory layout are identical. However, ina typical memory device, the cells at edges of a memory array often haveweaker electrical characteristics than their inner counterparts. One ofthe reasons causing the weaker edge cells is the loading effect, whichrefers to a phenomenon where the etch rate across a semiconductor wafervaries, as the pattern density varies over the surface of the wafer.These edge cells can have a smaller storage capacitance and drivingcurrent than those of the inner cells. In some cases, these weaker edgecells can adversely affect the yield rate of the memory devices.

As such, what is needed is a memory device with modified edge cells inorder to improve its performance and overall yield rate.

SUMMARY

The present invention discloses a memory macro with irregular edgecells. In one embodiment of the present invention, the memory macroincludes a first set of cells disposed in a first area of a memoryarray, and a second set of cells, which differ from the first set ofcells in physical dimensions, disposed at an edge of the first area forimproving robustness of the cells at the edge of the memory array.

The construction and method of operation of the invention, however,together with additional objectives and advantages thereof will be bestunderstood from the following description of specific embodiments whenread in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 partially illustrates a conventional memory macro.

FIG. 2 partially illustrates a memory macro in accordance with oneembodiment of the present invention.

FIG. 3 illustrates a layout diagram for a memory macro in accordancewith another embodiment of the present invention.

FIG. 4 illustrates a layout diagram for a memory macro in accordancewith yet another embodiment of the present invention.

FIG. 5 graphically illustrates the relation between the sense amplifiersize and the sensing margin.

FIG. 6 graphically illustrates the relation between the cell capacitanceand the sensing margin.

DESCRIPTION

FIG. 1 partially illustrates a conventional memory macro 100, whichincludes a memory array 105 with memory cells at intersections of rowsand columns. A first set of memory cells 106 (hereinafter also referredto as “the inner cells”) are disposed at an inner area of the memoryarray 105. A second set of memory cells 108 (hereinafter also referredto as “the edge cells”) are located at one or more edges of the memoryarray 105. The column decoder and sense amplifier 102 and the rowdecoder 104 are located at the end of columns and rows for selecting amemory cell for a read, write or erase operation.

In a design stage, all the memory cells, including the inner and edgecells 106 and 108, are identical to one another. However, the dimensionsof the edge cells 108 and the inner cells 106 may become different afterthe memory device 100 goes through various processing steps. Forexample, the loading effect may change the dimensions of the edge cells108. The changed dimensions make the edge memory cells 108 functiondifferently from the inner memory cells 106. For example, in a dynamicrandom access memory (DRAM) device, the edge cells may have lowercapacitance than those of the inner cells. For another example, in astatic random access memory (SRAM) device, the edge cells may produceless driving current than the inner cells. The weaker edge cells may, inturn, reduce the yield rate for the memory devices.

FIG. 2 partially illustrates a memory macro 200 in accordance with oneembodiment of the present invention. The memory macro 200 includes amemory array 205 with memory cells at intersections of rows and columns.The memory macro 200 can be a SRAM, DRAM, non-volatile memory ormagnetoresistive random access memory (MRAM). A first set of memorycells 206 (hereinafter also referred to as “the inner cells”) aredisposed at an inner area of the memory array 205. A second set ofmemory cells 208 (hereinafter also referred to as “the edge cells”) arelocated at one or more edges of the memory array 205. The column decoderand sense amplifier 202 and the row decoder 204 are located at the endof columns and rows for selecting a memory cell for a read, write orerase operation.

The proposed embodiment of the present invention allows the memory macro200 to better sustain process variations, such as the loading effectcaused by semiconductor processing technology, such as plasma etching orchemical mechanical polishing, during its fabrication stage. The innermemory cells 206 are designed to be regular cells, meaning that theyhave identical physical dimensions, construction rules and operationconditions. The edge memory cells 208 are designed to be irregularcells, meaning that they differ from the inner memory cells 206 inphysical dimensions, construction rules or operation conditions. Theirregular edge cells 206 allow the pattern at the edge of the memoryarray 205 to be different from that at the inner area thereof. Thus, theetch rate at the edge can be adjusted by carefully designing thephysical dimensions of the edge cells 208.

It is noted that while FIG. 2 shows one row and column of edge cells 208are arranged at the top and right edges of the memory array 205,respectively, the number of the rows and columns of the edge cells 208can vary. For example, it is within the spirit of the invention thateither a row or a column of edges cells 208 is disposed as long as itsatisfies design requirements. Likewise, two or more rows and columns ofedge cells 208 can also be used as required by designers.

The edge cells 208 can be designed as operative or inoperative cells.The chip size will be reduced if the edge cells 208 are designed asoperative. If the edge cells are operative, they would operate under oneor more conditions, such as the well bias, well pick-up bias, andground-node bias, which are independent from those for the inner cells206. The edge cells 208 can be designed with loosened rules, such thatthe electronic components in the edge cell 208 would be stronger thanthose in the inner cell 206. For example, a channel length or width of atransistor in the edge cell 208 can be larger than that of a transistorin the inner cell 206 by 5%. For a memory device made by 90 nmsemiconductor processing technology, a channel length or width of atransistor in the edge cell 208 can be larger than that of a transistorin the inner cell 206 by a range from 5% to 30%, to compensatevariations induced by the manufacturing process. For a memory devicemade by 65 nm semiconductor processing technology, a channel length orwidth of a transistor in the edge cell 208 can be larger than that of atransistor in the inner cell 206 by a range from 15% to 60%, tocompensate variations induced by the manufacturing process. The edgecell 208 can provide a larger storage node capacitance and a strongerdriving current.

The edge cells 208 can be designed to be inoperative. There are severalways to make the edge cells 208 as inoperative dummy cells. One way isto deliberately make the edge cells 208 incomplete. For example, theedge cells 208 can be designed to omit at least one critical layer, suchas an oxide defined (OD) layer and polysilicon layer, which is necessaryfor the same to be operative. For another example, the edge cells 208can be designed to omit at least one critical electronic component, suchas a pass gate transistor, pull-down device, and pull-up device, whichis necessary for the same to be operative. Alternatively, the edge cells208 can be constructed in the same way as other normal cells, but aredisabled from carrying out their functions. In all cases, the irregularedge cells 208 strengthen the robustness at the edge of memory array205.

FIG. 3 illustrates a layout diagram for a memory macro 300 in accordancewith another embodiment of the present invention. The layout diagram canbe generated by using an automated tool, such as a memory compiler. Thememory macro 300 includes a first area 302 and a second area 304 locatedat the edges thereof. The memory compiler can tile the first and secondareas with regular and irregular cells, respectively. The irregularcells can be the operable or inoperable cells discussed above. As such,the memory macro made based on the layout diagram can better sustain theprocess variations and improve its performance.

FIG. 4 illustrates a layout diagram for a DRAM macro 400 in accordancewith yet another embodiment of the present invention. The DRAM macro 400includes a memory array 402 with a plurality of sub-arrays havingregular memory cells 406 and sense amplifiers 408, which is comprised ofregular electronic components, adjacent to the regular memory cells. Thememory macro 400 further includes a sense amplifier 410, which iscomprised of irregular electronic components, at the edge of the memoryarray 402. The irregular electronic components can be operable orinoperable as discussed above. As such, the memory device made based onthe layout diagram can better sustain the process variations or improveits performance.

A exemplary relation between a memory array with edge memory cells and aread margin improvement for a 256 K-bit memory device using 4 columns ofedge cells is presented as follows:

TABLE 1 Edge cell type A B C Edge cell area 100 109 118 Read marginimprovement 100 106.436 114.78 Total area comparison 100 100.07 100.13

FIG. 5 graphically illustrates an exemplary relation between the senseamplifier size and the sensing margin. As the size of the senseamplifier increases, the mismatch becomes smaller, which leads to abetter sensing margin as illustrated in the graph.

FIG. 6 graphically illustrates the relation between the cell capacitanceand the sensing margin. As the cell size increases, the cell capacitanceincreases and results in a better sensing margin as illustrated in thegraph.

Manufacturing using the various technology nodes results in differentdimensions for the edge cells. The variation of the gate length and gatewidth between the inner memory cells and edge memory cells aftermanufacturing in the various technology nodes are estimated andpresented in the following table. The estimation is done for the 250 nm,180 nm, 130 nm, 90 nm and 65 nm technologies. In the table, the criticaldimension variation is the difference in the final channel length orwidth at the edge of the array to the final channel length or width atthe center of the array divided by the channel length or width as drawnon the mask. Based on the results, the channel length or widthcompensation is suggested for the edge cells for the various technologynodes.

TABLE 2 Tech. Node 250 nm 180 nm 130 nm  90 nm  65 nm Typical 356 nm 248nm 193 nm 193 nm 193 nm exposure wavelength CD variation ~4% ~3% ~4% ~8% ~15% (10/250) (5/180) (5/130) (8/100) (12/80) Row dimension Not NotNot >~5% >~5% compensation needed needed needed  5%–30% 15%–60% ColumnNot Not Not >~5% >~5% dimension needed needed needed  5%–30% 15%–60%compensation Area dimension Not Not Not 10%–60%  30%–130% compensationneeded needed needed

The above illustration provides many different embodiments orembodiments for implementing different features of the invention.Specific embodiments of components and processes are described to helpclarify the invention. These are, of course, merely embodiments and arenot intended to limit the invention from that described in the claims.

Although the invention is illustrated and described herein as embodiedin one or more specific examples, it is nevertheless not intended to belimited to the details shown, since various modifications and structuralchanges may be made therein without departing from the spirit of theinvention and within the scope and range of equivalents of the claims.Accordingly, it is appropriate that the appended claims be construedbroadly and in a manner consistent with the scope of the invention, asset forth in the following claims.

1. A method for generating a circuit layout for a memory macro having atleast one memory array to be used to fabricate a memory device, thememory array including a plurality of memory cells and sense amplifiers,comprising: generating a first set of memory cells and sense amplifierscomprised of regular electronic components disposed in a first area ofthe memory array, wherein the first area is disposed at an inner area ofthe memory array; and generating a second set of memory cells and senseamplifiers comprised of irregular electronic components disposed in asecond area located along an edge of the memory array, the second set ofmemory cells and sense amplifiers comprised of irregular electroniccomponents having different physical dimensions from those of the firstset of memory cells and sense amplifiers comprised of regular electroniccomponents to compensate for process-induced dimensional variations ofthe second set of memory cells and sense amplifiers, and wherein amemory compiler is used for generating the first and second sets ofmemory cells and sense amplifiers comprised of a predetermined number oftransistors of the of the circuit layout, and wherein a channel lengthor width of a transistor in the second set of cells is longer than thatof a transistor in the first set of cells so as to improve the operationspeed of the memory device.
 2. The method of claim 1, wherein a channellength or width of the transistor in the second set of cells is longerthan that of the transistor in the first set of cells by at least 5%. 3.The method of claim 1, wherein a channel length or width of thetransistor in the second set of cells is longer than that of thetransistor in the first set of cells by a range from about 5% to about30%.
 4. The method of claim 1, wherein the second set of cells areinoperative.
 5. The method of claim 1, wherein the second set of cellsare operative.
 6. The method of claim 1, wherein the second set of cellsomit at least one critical layer that is necessary for the second set ofcells to be operative.
 7. The method of claim 1, wherein the second setof cells omit at least one critical electronic component that isnecessary for the second set of cells to be operative.
 8. A memory macrohaving at least one memory array to be used to fabricate a memorydevice, comprising: a first set of memory cells and sense amplifierscomprised of regular electronic components disposed in a first arealocated in an inner area of a memory array; a second set of memory cellsand sense amplifiers comprised of irregular electronic componentsdisposed in a second area located along an edge of the memory array, thesecond set of memory cells and sense amplifiers comprised of irregularelectronic components having different physical dimensions from those ofthe first set of memory cells and sense amplifiers comprised of regularelectronic components to compensate for process-induced dimensionalvariations of the second set of memory cells, wherein each memory cellincludes a predetermined number of transistors; and a set of rowdecoders and column decoders configured to select a memory cell from thefirst and second sets of memory cells for a read or write operation ofthe memory macro, and wherein a channel length or width of a transistorin the second set of cells is longer than that of a transistor in thefirst set of cells so as to improve the operation speed of the memorydevice.
 9. The memory macro of claim 8, wherein a channel length orwidth of the transistor in the second set of cells is longer than thatof the transistor in the first set of cells by at least 5%.
 10. Thememory macro of claim 8, wherein a channel length or width of thetransistor in the second set of cells is longer than that of thetransistor in the first set of cells by a range from about 5% to about30%.
 11. The memory macro of claim 8 is a static random access memory(SRAM), dynamic random access memory (DRAM), non-volatile memory, ormagnetoresistive random access memory (MRAM).
 12. The memory macro ofclaim 8, wherein the second set of cells operate under one or moreconditions independent from those for the first set of cells.
 13. Thememory macro of claim 8, wherein the second set of cells are operative.14. The memory macro of claim 8, wherein the second set of cells areconstructed incompletely as opposed to the first set of cells.
 15. Amemory macro having at least one memory array to be used to fabricate amemory device, comprising: a first set of memory cells comprised ofregular electronic components disposed in a first area located in aninner area of a memory array; a second set of memory cells comprised ofirregular electronic components disposed in a second area located alongan edge of the memory array, the second set of memory cells havingdifferent physical dimensions from those of the first set of memorycells to compensate for process-induced dimensional variations of thesecond set of memory cells, wherein the memory array includes the firstand second areas, wherein each memory cell includes a predeterminednumber of transistors; a first sense amplifier disposed adjacent to oneside of the memory array away from the edge of the memory array; a setof row decoders and column decoders configured to select a memory cellfrom the first and second sets of memory cells for a read or writeoperation of the memory macro, and wherein the memory array includes atleast the first and second sets of memory cells, and wherein a channellength or width of a transistor in the second set of cells is longerthan that of a transistor in the first set of cells so as to improve theoperation speed of the memory device.
 16. The memory macro of claim 15is a dynamic random access memory (DRAM).
 17. The memory macro of claim15, wherein the second set of cells operates under one or moreconditions independent from those for the first sense amplifier.
 18. Thememory macro of claim 15, wherein a channel length or width of atransistor in the second set of cells is longer than that of atransistor in the first sense amplifier by at least 5%.
 19. The memorymacro of claim 15, wherein a channel length or width of a transistor inthe second set of cells is longer than that of a transistor in the firstset of cells by a range from about 5% to about 30%.
 20. The memory macroof claim 15, wherein the second set of cells are inoperative.